Non-volatile memory with improved programming and method therefor

ABSTRACT

Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.

FIELD OF THE INVENTION

[0001] This invention relates generally to non-volatile semiconductormemory such as electrically erasable programmable read-only memory(EEPROM) and flash EEPROM, and specifically to circuits and techniquesfor programming their memory states.

BACKGROUND OF THE INVENTION

[0002] Solid-state memory capable of nonvolatile storage of charge,particularly in the form of EEPROM and flash EEPROM, has recently becomethe storage of choice in a variety of mobile and handheld devices,notably information appliances and consumer electronics products. UnlikeRAM (random access memory) that is also solid-state memory, flash memoryis non-volatile, retaining its stored data even after power is turnedoff. In spite of the higher cost, flash memory is increasingly beingused in mass storage applications. Conventional mass storage, based onrotating magnetic medium such as hard drives and floppy disks, isunsuitable for the mobile and handheld environment. This is because diskdrives tend to be bulky, are prone to mechanical failure and have highlatency and high power requirements. These undesirable attributes makedisk-based storage impractical in most mobile and portable applications.On the other hand, flash memory is ideally suited in the mobile andhandheld environment because of its small size, low power consumption,high speed and high reliability features.

[0003] EEPROM and electrically programmable read-only memory (EPROM) arenon-volatile memory that can be erased and have new data written or“programmed” into their memory cells.

[0004] An EPROM utilizes a floating (unconnected) conductive gate, in afield effect transistor structure, positioned over a channel region in asemiconductor substrate, between source and drain regions. A controlgate is then provided over the floating gate. The threshold voltagecharacteristic of the transistor is controlled by the amount of chargethat is retained on the floating gate. That is, for a given level ofcharge on the floating gate, there is a corresponding voltage(threshold) that must be applied to the control gate before thetransistor is turned “on” to permit conduction between its source anddrain regions.

[0005] The floating gate can hold a range of charge and therefore anEPROM memory cell can be programmed to any threshold voltage levelwithin a threshold voltage window. The size of the threshold voltagewindow is delimited by the minimum and maximum threshold levels of thedevice, which in turn correspond to the range of the charges that can beprogrammed onto the floating gate. The threshold window generallydepends on the memory device's characteristics, operating conditions andhistory. Each distinct, resolvable threshold voltage level range withinthe window may, in principle, be used to designate a definite memorystate of the cell.

[0006] For EPROM memory, the transistor serving as a memory cell istypically programmed to a programmed state by accelerating electronsfrom the substrate channel region, through a thin gate dielectric andonto the floating gate. The memory is bulk erasable by removing thecharge on the floating gate by ultraviolet radiation.

[0007]FIG. 1A illustrates schematically a non-volatile memory in theform of an EEPROM cell with a floating gate for storing charge. Anelectrically erasable and programmable read-only memory (EEPROM) has asimilar structure to EPROM, but additionally provides a mechanism foradding and removing charge electrically from its floating gate uponapplication of proper voltages without the need for exposure to UVradiation.

[0008] An array of such EEPROM cells is referred to as a “Flash” EEPROMarray when an entire array of cells, or significant group of cells ofthe array, is electrically erased together (i.e., in a flash). Onceerased, the group of cells can then be reprogrammed.

[0009]FIG. 1B illustrates schematically a non-volatile memory in theform of a NROM cell with a dielectric layer for storing charge. Insteadof storing charge in a floating gate, it has a dielectric layer forstoring charge. For example; U.S. Pat. Nos. 5,768,192 and 6,011,725disclose a nonvolatile memory trapping dielectric sandwiched between twosilicon dioxide layers.

CELL AND ARRAY STRUCTURE

[0010]FIG. 1C illustrates schematically a flash EEPROM cell having botha select gate and a control or steering gate. Memory devices having sucha cell structure are described in U.S. Pat. No. 5,313,421, which patentis incorporated herein by reference. The memory cell 10 has a“split-channel” 12 between source 14 and drain 16 diffusions. A cell isformed effectively with two transistors T1 and T2 in series. T1 servesas a memory transistor having a floating gate 20 and a control gate 30.The control gate will also be referred to as a steering gate 30. Thefloating gate is capable of storing a selectable amount of charge. Theamount of current that can flow through the T1's portion of the channeldepends on the voltage on the steering gate 30 and the amount of chargeresiding on the intervening floating gate 20. T2 serves as a selecttransistor having a select gate 40. When T2 is turned on by a voltage atthe select gate 40, it allows the current in the T1's portion of thechannel to pass between the source and drain.

[0011]FIG. 1D illustrates schematically another flash EEPROM cell havingdual floating gates and independent select and control gates. Memorydevices having such a cell structure are described in co-pending U.S.patent application Ser. No. 09/343,493, filed Jun. 30, 1999, whichdisclosure is incorporated herein by reference. The memory cell 10′ issimilar to that of FIG. 1C except it effectively has three transistorsin series. Between a pair of memory transistors, T1-left and T1-right,is a select transistor T2. The memory transistors have floating gates20′ and 20″ and steering gates 30′ and 30″ respectively. The selecttransistor T2 is controlled by a control gate 40′. At any one time, onlyone of the pair of memory transistors is accessed for read or program.When the storage unit T1 -left is being accessed, both the T2 andT1-right are turned on to allow the current in the T1-left's portion ofthe channel to pass between the source and the drain. Similarly, whenthe storage unit T1-right is being accessed, T2 and T1-left are turnedon. Erase is effected by having a portion of the select gate polysiliconin close proximity to the floating gate and applying a substantialpositive voltage (e.g. 20V) to the select gate so that the electronsstored within the floating gate can tunnel to the select gatepolysilicon.

[0012]FIG. 2 is a schematic block diagram of an addressable array ofmemory cells in rows and columns with decoders. A two-dimensional arrayof memory cells 100 is formed, with each row of memory cells connectingby their sources and drains in a daisy-chain manner. Each memory cell 50has a source 54, a drain 56 and a steering gate 60 and a select gate 70.The cells in a row have their select gates connected to a word line 110.The cells in a column have their sources and drains respectivelyconnected to bit lines 124, 126. The cells in a column also have theirsteering gates connected by a steering line 130.

[0013] When the cell 50 is addressed for programming or reading,appropriate programming or reading voltages (V_(S), V_(D), V_(STG),V_(SLG)) must be supplied respectively to the cell's source 54 and drain56, steering gate 60 and select gate 70. A word line decoder 112selectively connects a selected word line to a select voltage V_(SLG). Abit line decoder 122 selectively connects the pair of bit lines 124, 126in an addressed column respectively to source voltage V_(S) and drainvoltage V_(D). Similarly, a steering line decoder 132 selectivelyconnects the steering line 130 in the addressed column to a steering orcontrol gate voltage V_(STG).

[0014] Thus, a specific cell of the two-dimensional array of flashEEPROM cells is addressed for programming or reading by a selection ordecode in the column direction of a pair of bit lines and a steeringline, and in the row direction of a word line. In order to increaseperformance, the column decoders 122 and 132 allow a group of columns tobe selected, and therefore a corresponding group or chunk of cells to beaccessed in parallel, thereby accessing the row of cells chunk-by-chunk.

[0015] Previously, many flash EEPROM devices have had a word lineconnecting all the control gates of cells along each row. Thus, the wordline essentially performs two functions: row selection; and supplyingcontrol gate voltage to all cells in the row for reading or programming.It is often difficult to perform both of these functions in an optimummanner with a single voltage. If the voltage is sufficient for rowselection, it may be higher than desirable for programming. However,with a cell having independent steering gate and select gate, the wordline which is connected to the select gates of cell in a row need onlyperform the selection function while the steering line performs thefunction of supplying optimum, independent control gate voltage toindividual cells in a column.

CELL CHARACTERISTICS

[0016] In the usual two-state EEPROM cell, at least one currentbreakpoint level is established so as to partition the conduction windowinto two regions. When a cell is read by applying predetermined, fixedvoltages, its source/drain current is resolved into a memory state bycomparing with the breakpoint level (or reference current I_(REF)). Ifthe current read is higher than that of the breakpoint level or I_(REF),the cell is determined to be in one logical state (e.g., a “zero”state), while if the current is less than that of the breakpoint level,the cell is determined to be in the other logical state (e.g., a “one”state). Thus, such a two-state cell stores one bit of digitalinformation. A reference current source, which may be externallyprogrammable, is often provided as part of a memory system to generatethe breakpoint level current.

[0017] In order to increase memory capacity, flash EEPROM devices arebeing fabricated with higher and higher density as the state of thesemiconductor technology advances. Another method for increasing storagecapacity is to have each memory cell store more than two states.

[0018] For a multi-state or multi-level EEPROM memory cell, theconduction window is partitioned into more than two regions by more thanone breakpoint such that each cell is capable of storing more than onebit of data. The information that a given EEPROM array can store is thusincreased with the number of states that each cell can store. EEPROM orflash EEPROM with multi-state or multi-level memory cells have beendescribed in U.S. Pat. No. 5,172,338.

[0019] In practice, the memory state of a cell is usually read bysensing the conduction current across the source and drain electrodes ofthe cell when a reference voltage is applied to the control gate. Thus,for each given charge on the floating gate of a cell, a correspondingconduction current with respect to a fixed reference control gatevoltage may be detected. Similarly, the range of charge programmableonto the floating gate defines a corresponding threshold voltage windowor a corresponding conduction current window.

[0020] Alternatively, instead of detecting the conduction current amonga partitioned current window, it is possible to determine the thresholdvoltage at the control gate that causes the conduction current to just“trip” or transverse a fixed reference current. Thus, the detection isperformed on a threshold voltage among a partitioned threshold voltagewindow.

[0021]FIG. 3 illustrates the relation between the source-drain currentI_(D) and the control gate voltage V_(STG) for four different chargesQ1-Q4 that the floating gate may be selectively storing at any one time.The four solid I_(D) versus V_(STG) curves represent four possiblecharge levels that can be programmed on a floating gate of a memorycell, respectively corresponding to four possible memory states. As anexample, the threshold voltage window of a population of cells may rangefrom 0.5V to 3.5V. Six memory states may be demarcated by partitioningthe threshold window into five regions in interval of 0.5V each. Forexample, if a reference current, I_(REF) of 2 μA is used as shown, thenthe cell programmed with Q1 may be considered to be in a memory state“1” since its curve intersects with I_(REF) in the region of thethreshold window demarcated by V_(STG)=0.5V and 1.0V. Similarly, Q4 isin a memory state

[0022] As can be seen from the description above, the more states amemory cell is made to store, the more finely divided is its thresholdwindow. This will require higher precision in programming and readingoperations in order to be able to achieve the required resolution.

[0023] U.S. Pat. No. 4,357,685 discloses a method of programming a2-state EPROM in which when a cell is programmed to a given state, it issubject to successive programming voltage pulses, each time addingincremental charge to the floating gate. In between pulses, the cell isread back or verified to determine its source-drain current relative tothe breakpoint level. Programming stops when the current state has beenverified to reach the desired state. The programming pulse train usedmay have increasing period or amplitude.

[0024] Prior art programming circuits simply apply programming pulses tostep through the threshold window from the erased or ground state untilthe target state is reached. Practically, to allow for adequateresolution, each partitioned or demarcated region would require at leastabout five programming steps to transverse. The performance isacceptable for 2-state memory cells. However, for multi-state cells, thenumber of steps required increases with the number of partitions andtherefore, the programming precision or resolution must be increased.For example, a 16-state cell may require on average at least 40programming pulses to program to a target state.

SUMMARY AND OBJECTS OF THE INVENTION

[0025] Accordingly, it is a general object of the present invention toprovide high density and high performance, yet low cost memory device.

[0026] In particular, it is a general object of the present invention toprovide high performance flash EEPROM that can support memory statessubstantially greater than two.

[0027] It is another general object of the present invention to provideflash EEPROM semiconductor chips that can replace magnetic disk storagedevices in computer systems.

[0028] It is an object of the present invention to provide improvedprogramming circuits and methods for flash EEPROM devices.

[0029] It is also an object of the invention to provide programmingcircuits that are simpler and easier to manufacture and have improvedaccuracy and reliability over an extended period of use.

[0030] These and additional objects are accomplished by improvements inprogramming circuits and techniques for nonvolatile floating gatedevices. Various aspects of the present invention help to increaseperformance while achieving the required fine programming resolution.One feature of the present invention is to use programming pulses withmagnitudes optimized for the data to be programmed (target state) sothat within the first step or first few steps, the cell is programmed asclose to the target state as possible without overshooting. A secondfeature is to iterate the programming through a series of operationphases, where with each phase the programming waveform producesincreasing finer programming steps. Another feature is to implement thefirst two features in a programming operation applicable to a group ofcells in parallel. In this way, both high resolution and rapidconvergence to the target state can be achieved at the same time whileparallel operation further improves performance.

[0031] According to one aspect of the invention, in a memory device withmultistate cells, the improvement includes a programming circuit andmethod that can be applied to a group of memory cells in parallel. Theprogramming pulses applied to each of the cells in parallel areoptimized for the data to be stored in that cell. In this way, each ofthe cells is programmed to its target state with a minimum ofprogramming pulses. In the preferred embodiment, this is accomplished byprovision of a programming voltage bus supplying a plurality of voltagelevels and the programming circuit for each cell in the group able toselect from the voltage bus an optimum voltage level appropriate forprogramming each cell to its target state.

[0032] According to another aspect of the invention, the programmingpulses are applied over a plurality of programming operation phases,with increasingly finer programming resolution. In the preferredembodiment, during each phase, a programming voltage in the form of astaircase waveform is applied to each of the cells in parallel. A cellin the group is excluded from further programming when it has beenprogrammed to pass a predetermined level offset short of the targetlevel corresponding to the target state. The offset is such that aprogramming pulse that programs a cell past the predetermined level doesnot overshoot the target level by more than a predetermined margin. Thepredetermined margin is implicitly set by the size of the programmingsteps. During the last phase, the predetermined level is the same as thetarget level with the offset being zero. In this way, rapid convergenceto the target state is possible while achieving high resolution.

[0033] The improved programming circuits and techniques allow the rangeof conduction states or threshold voltages of the cell to be finelypartitioned to support higher density storage. In the preferredembodiment, a flash EEPROM cell with 16 distinct states can beprogrammed within about 10-20 programming steps. When the improvedfeatures of data-dependent programming voltages and multiphaseprogramming are implemented in a massively parallel operation, a highdensity and high performance, yet low cost flash EEPROM is possible.Additional objects, features and advantages of the present inventionwill be understood from the following description of its preferredembodiments, which description should be taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034]FIG. 1A illustrates schematically a non-volatile memory in theform of an EEPROM cell.

[0035]FIG. 1B illustrates schematically a non-volatile memory in theform of a NROM cell.

[0036]FIG. 1C illustrates schematically a flash EEPROM cell having botha select gate and a control or steering gate.

[0037]FIG. 1D illustrates schematically another flash EEPROM cell havingdual floating gates and independent select and control gates.

[0038]FIG. 2 is a schematic block diagram of an addressable array ofmemory cells in rows and columns with decoders.

[0039]FIG. 3 illustrates the relation between the source-drain currentI(t) and the control gate voltage V_(STG) for four different chargesQ1-Q4 that the floating gate may be storing at any one time.

[0040]FIG. 4 is a block diagram illustrating a programming system forprogramming a group of memory cells in parallel, according to apreferred embodiment of the present invention.

[0041]FIG. 5 shows in more detail the multiphase program voltagegenerator and the cell program controller of the multiphase programmingcircuit of FIG. 4.

[0042] FIGS. 6(a)-6(e) are timing diagrams for the sample and holdoperation of the multiphase program voltage generator of FIG. 5.

[0043] FIGS. 7(a)-7(i) are timing diagrams for the first phase'soperation of the multiphase program voltage generator shown in FIG. 5.

[0044] FIGS. 8(a)-8(j) are timing diagrams for the second phase'soperation of the multiphase program voltage generator shown in FIG. 5.

[0045]FIG. 9 is a flow diagram of the multiphase, parallel programmingof a group of memory cells, according to a preferred embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046]FIG. 4 is a block diagram illustrating a programming system forprogramming a group of memory cells in parallel, according to apreferred embodiment of the present invention. The programming system200 comprises a bank of multiphase programming circuits 210, . . . ,210′ for supplying optimized individual programming voltages V_(STG)(1),. . . , V_(STG)(k) to the steering gates 60, . . . , 60′ of a group of kmemory cells, 50, . . . , 50′. In one preferred embodiment, a chunk sizeof k=4096 cells is programmed in parallel.

[0047] The multiphase programming circuit 210 essentially supplies aseries of programming voltage pulses to the steering gate of cell 50.When the cell 50 is to be programmed to a target state S₁, the suppliedvoltage pulses are optimized to program the cell to S₁ accurately andquickly. In one preferred embodiment, the threshold window of each cell50 is partitioned to designate one of sixteen states. For example, acell spanning a threshold voltage window between 0.5-3.5V would requirepartitioning into approximately 0.2V intervals to demarcate 16 states.This is approximately one order of magnitude higher than the resolutionused in a 2-state partitioning.

[0048] A multi-voltage bus 220 is driven by a power supply 222 toprovide a plurality of optimum starting voltages V₀, for programming andreading the partitioned states. In general, the more voltages available,the finer is the optimization of the starting voltages. In the preferredembodiment, the multi-voltage bus will supply voltages approximately thesame as each of the partitioned threshold voltages. In the presentexample, the bus comprises 16 power lines with voltages being 0.4, 0.6,0.8, 1.0, 1.2, 1.4, 1.6, 1.8, 2.0, 2.2, 2.4, 2.6, 2.8, 3.0, 3.2, and3.4V.

[0049] When the cell 50 is to be programmed to a target state S₁, thedata is stored in a data latch 232. A voltage selector 230, responsiveto the target state data D(S₁) (which may be multiple bits) in the datalatch 232, selects one of the bus line voltages, V₀(S₁) which isoptimized for programming the cell to the target state S₁.

[0050] As described earlier, programming is accomplished by alternatelyapplying a programming pulse to the cell followed by reading back todetermine the resultant memory state of the cell. During verify (readback) operations, the voltage V₀(S₁) is applied to the cell's steeringgate 60. During programming the voltage V₀(S₁) forms the basis forconstructing a programming voltage having a predetermined waveformprofile. Depending on the desired programming rate, the waveform profilecan be a flat one to increasing ones resulting in increasing rate ofprogramming. In one preferred embodiment the predetermined waveformprofile is a staircase waveform.

[0051] During a verify operation, a signal VERIFY enables a path 234 forV₀(S₁) from the voltage selector 230 to be supplied to the steering gate60 of the cell 50. The resultant source-drain current is compared to areference current by a sense amplifier 240. Prior to the start ofprogramming, the cell 50 is in an erased state where the source-draincurrent is larger than the reference current. As the cell 50 isprogressively being programmed, charges accumulate on the floating gatethereby diminishing the field effect of the steering gate's V₀(S₁) onthe channel so that the source-drain current decreases until it dropsbelow that of the reference current, I_(REF) during verify. At thatpoint the cell has been programmed to a desired level, and the event issignaled by an output signal PASSED* from the sense amplifier 240 goingLOW.

[0052] During a programming operation, a multiphase program voltagegenerator 250 uses V₀(S₁) to form the basis for generating variouswaveforms to be supplied to the steering gate 60 of the cell. Themultiphase program voltage generator 250 generates different waveformsunder different operating phases and is controlled by a cell programcontroller 260 that is responsive to the state of the local cell 50 aswell as the states of all the cells in the group of k cells.

[0053] The cell program controller 260 is also responsive to the outputsignal of the sense amplifier 240. As described above, when the cell isprogrammed to a desired level, the sense amplifier's output signal,PASSED*, goes LOW which in turn causes the controller 260 to output asignal PGM₁* to enable a program inhibit circuit 280. When enabled, theprogram inhibit circuit 280 essentially inhibits the cell 50 fromfurther programming by applying appropriate voltages to the drain andsteering gates.

[0054] For programming k cells in parallel, a bank of multiphaseprogramming circuits, 210, . . . , 210′ is employed, one programmingcircuit for each cell. A parallel program controller 290, responsive tothe status PGM₁*, . . . , PGM_(k)* from each of the k multiphaseprogramming circuit cells, coordinates the programming operations of thebank of programming circuits. As will be described in more detail later,a new phase begins after all the k cells have been programmed to theirrespective desired levels, equivalent to each cell tripping its senseamplifier's reference current. This results in PGM₁* to PGM_(k)* allhaving become LOW.

[0055]FIG. 5 shows in more detail the multiphase program voltagegenerator 250 and the cell program controller 260 of the multiphaseprogramming circuit 210 of FIG. 4. The operation of the variouscomponents is best described in combination with the timing diagramsshown in FIGS. 6-8.

[0056] Essentially, the multiphase program voltage generator 250, in aninitial phase of the operation as designated by a control signal SAMPLEpulsing HIGH, samples and stores the optimized voltage V₀(S₁) in asample-and-hold circuit 300. The sample-and-hold circuit 300 has anoutput node 307 where voltages from other sources (such as 330, 350 tobe described below) are summed to form a resultant voltage, VLast. Thisvoltage, VLast, then drives a source follower 310 to provide theprogramming voltage V_(STG)(1) at the steering gate of the cell 50.

[0057] The sample-and-hold circuit 300 comprises an input gated by twoseries transistors 302, 304 with a common node 303 in between and theoutput node 307. The common node 303 can be set to a voltage V_(HOLD)gated by another transistor 308.

[0058] In the preferred embodiment, the other sources of voltages thatare summed at the output node 307 to produce VLast are generated by afirst-phase waveform generator 320 with an associated AC coupler 330 anda second-phase waveform generator 340 with an associated AC coupler 350.

[0059] FIGS. 6(a)-6(e) are timing diagrams for the sample and holdoperation of the multiphase program voltage generator of FIG. 5. Inoperation, the parallel program controller 290 (see FIG. 4) asserts theSAMPLE signal that turns on the two series transistors 302 and 304 toallow input voltage V₀(S₁) to be sustained across a capacitor C₁, of theAC coupler 330. In the sample and hold operation, the waveformgenerators 320 and 340 do not contribute to Vlast as their paths areblocked by the gating signals G₁ and G₂ (FIG. 6(c)) respectively. Thus,the voltage, Vlast, at the output node 307 initially assumes the valueof V₀(S₁) (FIG. 6(e)). Thereafter, the two series transistors are turnedoff with SAMPLE going LOW (FIG. 6(a)) and the common node 303 is allowedto acquire the voltage V^(HOLD) after a signal HOLD (FIG. 6(b)) isasserted on the gate of the transistor 308. This debiasing arrangementreduces the leakage of VLast back through transistor 304 by severalorders of magnitude and ensures the accuracy of the sampled voltagestored at the node 307.

[0060] The cell program controller 260 shown in FIG. 5 comprises aSet/Reset latch 262. When the cell 50 has been programmed to have itsconduction current below a reference current level, the sense amplifieroutputs the signal PASSED* going from HIGH to LOW. This is used to setthe set-reset latch 262 to change a latched output signal PGM₁* fromHIGH to LOW, which in turn enables the program inhibit circuit 280.

[0061] FIGS. 7(a)-7(i) are timing diagrams for the first phase'soperation of the multiphase program voltage generator shown in FIG. 5.In the preferred embodiment, a verify operation is performed prior toprogramming. A RESET signal resets the set-reset latch 262 so that thelatched output signal PGM₁* is HIGH. A verify operation is enabledwhenever the VERIFY signal goes HIGH. Conversely, a programmingoperation can take place when the VERIFY signal is LOW. If the cell 50is properly erased, the sense amplifier 240's output signal PASSED* willbe HIGH, which allows programming to take place because it will notactivate the program inhibit circuit 280. (See also FIG. 4.) During thefirst phase of the programming operation, the first waveform generator320 is enabled by a control signal Φ₁ (FIG. 7(e)) from the parallelprogram controller 290. It then generates V₁(t) (FIG. 7(h)) in the formof one or more staircase pulses when the pass-gate signal G₁ isenabling. The initial rise of the first pulse is preferably ramped tomoderate the otherwise steep rise thereby tempering any undesirablestress to the memory cell. Each successive pulse of the waveform willmove the programmed level of the cell towards a target level, which isset to be a preferred level designating the target state for the cell.Because of the discrete nature of the programming steps, there will be astatistical distribution of programmed levels designated to berepresenting a given memory state. In the present embodiment, a cell isconsidered to be programmed to a given memory state when the programmedthreshold level falls within the range of programmed levels associatedwith that state. The range of programmed levels is delimited at the lowend by the target level and at the high end by the predetermined marginassociated with that state.

[0062] In order to avoid overshooting the range of programmed levels,the programming circuit uses a predetermined level, short of the range,to gauge when to halt programming during each phase. This predeterminedlevel is offset short of the target level such that when a programmingpulse moves the programmed level past the predetermined level, it willnot exceed the target level by more than the associated predeterminedmargin. In other words, once the predetermined level is passed, the cellis programmed to a level not exceeding the high end of the program levelrange for that state. In that event, the programming pulses of thecurrent phase will no longer be applied. Thus, the considerations forthe rate of increase of the staircase waveform and the first-phasepredetermined level are as follows. The target level is approached withsuccessive pulses as quickly as possible but no single pulse will causethe memory cells' threshold to pass both the first-phase predeterminedlevel and the associated predetermined margin beyond the target level.

[0063] V₁(t) is enabled at a node 333 by the control signal PGM₁* beingHIGH and is added via the AC coupler 330 to the output node 307. (SeeFIGS. 7(d), 7(h).) Thus, the voltage at the output node 307 isVLast=V₀(S₁)+b₁V₁(t) (where b₁ is a coupling ratio near unity) and itpasses through the source follower 310 to become the voltage supplied tothe steering gate of the cell 50. (See FIG. 7(i).) As programming pulsesare successively applied, eventually, the cell 50 is programmed to thepredetermined level for the first phase. At this point the signalPASSED* (FIG. 7(c)) goes LOW and in turn causes the signal PGM₁* to goLOW (FIG. 7(d)) which in turn enables the program inhibit circuit 280 toinhibit the cell 50 from further programming. At the same time, PGM₁*going LOW causes G₁ to go LOW (FIG. 7(f)), which cuts off the AC coupler330 from the first waveform generator 320, thereby freezing V₁ at theamplitude of the waveform at the time of cutoff. If T_(1f) is the timewhen PGM₁* goes LOW, then V₁=V₁(T_(1f)), so that VLast(T_(1f))=V₀(S₁)+b₁V₁(T_(1f)).

[0064] In the meantime, parallel programming for other cells in thechunk continues while more and more of the cells reach their associatedfirst-phase predetermined level and drop out of the parallel programmingoperation. As each cell drop out, each of their associated VLast retainsthe corresponding voltage applied to the steering gate at the time ofprogram inhibition. Eventually, all cells in the chunk become programmedto the corresponding predetermined levels and this event is signaled byPGM₁* to PGM_(k)* all having become LOW. This will prompt the parallelprogram controller 290 to initiate the next phase.

[0065] FIGS. 8(a)-8(i) are timing diagrams for the second phase'soperation of the multiphase program voltage generator shown in FIG. 5.The second phase is similar to the first phase, starting with verifyperformed prior to programming, except the first waveform generator isdisabled by the control signal Φ₁ being LOW (FIG. 8(e)). Instead, thesecond waveform generator 340 is enabled by a control signal Φ₂ (FIG.8(f)) from the parallel program controller 290 and generates V₂(t) inthe form of one or more staircase pulses (FIG. 8(i)). Each successivepulse of the waveform will move the programmed level of the cell towardsa second-phase predetermined level offset from the target level. Therate of increase of the staircase waveform and the second-phasepredetermined level are such that the target level is approached withsuccessive pulses as quickly as possible but no single pulse will causethe memory cells' threshold to pass both the second-phase predeterminedlevel and the associated predetermined margin beyond the target level.In general the rate of increase of the staircase waveform and thepredetermined level will be much finer than those of the first phase.

[0066] V₂(t) is enabled at a node 335 by a reset control signal PGM₁*being HIGH (FIG. 8(d)) (with all the SR latches having been reset at thestart of the second phase (FIG. 8(a)) and is added via the AC coupler350 to the node 333. Thus, the voltage at the output node 307 isVLast=V₀(S₁)+b₁[V₁(T_(1f))+b₂[V₂(t)−V_(2i)], where b₂ is anothercoupling ratio, and V_(2i) is the value of V₂ when G1 goes LOW and is apredetermined offset (e.g. ˜0.4V) applied before the end of the firstphase. VLast passes through the source follower 310 to become thevoltage supplied to the steering gate of the cell 50. (See FIG. 8(j).)As programming pulses are successively applied, eventually, the cell 50is programmed to the predetermined level for the current phase. At thispoint the signal PASSED* (FIG. 8(c)) goes LOW and in turn causes thesignal PGM₁* to go LOW (FIG. 8(d)) which in turn enables the programinhibit circuit 280 to inhibit the cell 50 from further programming. Atthe same time, PGM₁* going LOW causes G2 to go LOW (FIG. 8(g)), whichcuts off the AC coupler 350 from the second waveform generator 340 bydisabling control signal G2, thereby freezing V₂ at the amplitude of thewaveform at the time of cutoff. If T_(2f) is the time when PGM₁* goesLOW, then V₂=V₂(T_(2f)), so that VLast (T_(2f))=V₀(S₁)+b₁V_(1(T)_(1f))+b₂[V₂(T_(2f))−V_(2i)].

[0067] Similarly, parallel programming for other cells in the chunkcontinues while more and more of the cells reach their target states anddrop out of the parallel programming operation and each of their VLastretains the voltage applied to the steering gate at the time of programinhibition. Eventually, all cells in the chunk have been programmed tothe predetermined level and this event is signaled by PGM₁* to PGM_(k)*all having become LOW. This will prompt the parallel program controller290 to initiate the next phase.

[0068] Similar arrangement applies to higher phases, where a waveformgenerator produces a voltage that is added to the level of VLast frozenat the end of the previous phase. At the last phase, the predeterminedlevel is the same as the target level corresponding to the target state.

[0069] In another embodiment, VLast is generated by one multi-phasewaveform generator.

[0070] The implementation of multiphase programming allows for differentrates of increase of the staircase waveform during the different phases.The target state to be programmed is approached by a hierarchy ofprogramming steps, with the first phase being the coarsest, approachingthe target state in the fewest steps without over--shooting, thenfollowing by the next phase with a series of finer steps, again,approaching further the target state in the fewest steps withoutover-shooting, and so on. In this way, a series of increasingprogramming pulses is applied to the steering gate 60 of the cell 50,with the rate of increase during each phase being optimized for rapidconvergence to the target state.

[0071] As described above, for each phase short of the final phase, alevel short of the target state is used as the target, such thatcrossing it in a programming step for that phase will not lead toovershooting the actual target state. In the final phase, the target isthe actual target state. In the preferred embodiment, thephase-dependent level is implemented by shifting down a predeterminedamount the voltage applied to a steering gate V_(STG) during the verifyoperation. This will result in the sense amplifier 240 (see FIG. 4)tripping before the actual target state is reached. The power source222, (see FIG. 4), responsive to the state of the phase, adjusts thevoltages on the multi-voltage bus 220 accordingly.

[0072] In an alternative embodiment, the phase-dependent verifying isaccomplished by adjusting the reference current I_(REF) employed by thesense amplifier 240, shown in FIG. 4, to incrementally lower values.

[0073] In yet another embodiment, the phase-dependent verifying isaccomplished by a combination of shifting down a predetermined amountthe voltage applied to the steering gate during the verify operation andadjusting the reference current employed by the sense amplifier.

[0074] A number of embodiments have been found to allow programming toconverge to a target state within about 10-20 steps or so for a cellpartitioned into 16 states. For example, one preferred embodiment has atwo-phase programming operation, the first phase having a firstincreasing waveform followed by a second phase with a second more gentlyincreasing waveform. Another embodiment has a three-phase operation withthe first being a single pulse, followed by two series of staircasewaveforms. Various combinations are possible and are contemplated by theinvention.

[0075] One advantage of the programming system 200 described is eventhough a large group of cells are being programmed in parallel, thecells can all share the same power bus 220 to realize data-dependentprogramming voltages. Similarly, the phase-dependent waveform generatorssuch as 320, 340, . . . are shared by all the cells in the group.

[0076]FIG. 9 is a flow diagram of the multiphase, parallel programmingof a group of memory cells, according to a preferred embodiment of thepresent invention. Step 400: BEGIN INITIALIZATION, Set Phase=0,PhaseLast=2 (as an example)

[0077] Step 410: BEGIN GETTING DATA-DEPENDENT VOLTAGE

[0078] Step 412: Do the chunk of cells, i=1 to k, in parallel

[0079] Step 414: Latch D(S_(i)), the ith cell's target state.

[0080] Step 416: Use D(S_(i)) to select an initial voltage,V₀(D(S_(i))), optimized for programming the ith cell to D(S_(i)).

[0081] Step 418: Store V₀(D(S_(i))) to be used as a baseline voltage forthe steering gate voltage, i.e., VLast(i)=V₀(D(S_(i))).

[0082] Step 420: BEGIN NEW PHASE OF PARALLEL PROGRAMMING

[0083] Step 422: Phase=Phase+1

[0084] Step 430: BEGIN CHUNK PROGRAMMING, i=1 to k in parallel

[0085] Step 432: Set steering gate voltage to a phase-dependent waveformrelative to the baseline VLast(i).

[0086] Step 434: Continue programming the chunk of cells in parallel.

[0087] Step 436: Verify to see if the ith cell has been programmed towithin a predetermined level of the target state. The level is phasedependent and sufficiently short of the target state such that aprogramming step that crosses the level does not overshoot the targetstate. If the level has been passed, proceed to Step 440, if notcontinue to Step 438.

[0088] Step 438: Apply a programming pulse V_(STG)(i) to the ith cell.Return to Step 436.

[0089] Step 440: Inhibit ith cell from further programming during thecurrent phase.

[0090] Step 442: Store the current programming voltage, i.e.VLast(i)=V_(STG)(i) as a baseline voltage for the next phase.

[0091] Step 450: Are all cells programmed past the level for the currentphase? If that is the case, proceed to Step 460. Otherwise return toStep 434 to continue programming the remaining cells in the chunk untilthe last one has passed the level of the current phase. If programminghas passed a predetermined maximum allowed number of pulses, apredetermined exception handling is initiated and where typically anerror handling routine sets in.

[0092] Step 460: Is Phase=PhaseLast? If not, proceed to Step 420 tobegin the next phase. Otherwise proceed to Step 470.

[0093] Step 470: DONE. Programming of the chunk of cells i=1 to k iscompleted.

[0094] The embodiments of the present invention have been discussed inreference to non-volatile semiconductor memory that contains a chargestoring floating gate or dielectric layer. However, the various aspectsof the present invention may be applied to any type of non-volatilememory where precise programming may be performed through theapplication of state-dependent, optimally controlled voltage programmingpulses. For example, this methodology can be applied to multi-dielectricstorage devices, such as Metal Nitride Oxide Silicon (MNOS) orPolysilicon Nitride Oxide Silicon (SONOS) devices. Similarly, it isapplicable to MROM devices.

[0095] While the embodiments of this invention that have been describedare the preferred implementations, those skilled in the art willunderstand that variations thereof may also be possible. Therefore, theinvention is entitled to protection within the full scope of theappended claims.

What is claimed is:
 1. A method of programming a group of memory cellsin parallel, each memory cell having a charge storage individuallyprogrammable to a target charge level corresponding to a target memorystate among a plurality of memory states thereof, comprising: providinga plurality of voltage levels for programming a memory cell to one ofsaid plurality of memory states; selecting one of said plurality ofvoltage levels for each memory cell of the group, the selected voltagelevel being a function of the memory cell's target memory state;generating a programming voltage as function of the selected voltage foreach memory cell; and programming the group of memory cells in parallel.2. A method as in 1, further comprising: generating a programmingvoltage waveform for each cell of said group, each said programmingvoltage waveform having an initial amplitude which is a function of saidvoltage level selected for each cell.
 3. A method as in 2, wherein saidprogramming voltage waveform includes a series of voltage pulses.
 4. Amethod as in 3, wherein applying an initial one of said series ofvoltage pulses programs each cell substantially towards but notovershooting its target memory state.
 5. A method as in 3, wherein saidseries of voltage pulses has an amplitude that increases with time.
 6. Amethod as in 3, further comprising: (a) programming said group of memorycells in parallel by applying to each cell a pulse from said series ofvoltage pulses of the programming voltage waveform associated with eachcell; (b) verifying said group of memory cells in parallel bydetermining if each cell has been programmed to a predetermined levelassociated with the target state of each memory cell, (c) inhibiting anycell from said group from further programming when said any cell hasbeen programmed to its predetermined level; and (d) repeating (a), (b)and (c) until all cells in said group have been programmed to theirrespective predetermined levels.
 7. A method as in 6, wherein saidrepeating step also terminates when it has iterated more than apredetermined number of times.
 8. A method as in 6, wherein saidrepeated cycling of (a)-(d) until termination constitutes oneprogramming phase, and said method further comprises one or moreadditional programming phases, each with its associated series ofvoltage pulses and predetermined levels.
 9. A method as in 8, whereineach successive phase employs a series of voltage pulses that produce afiner programming step from the previous phase.
 10. A method as in 8,wherein each successive phase employs predetermined levels that arecloser to the target states.
 11. A method as in 8, wherein apredetermined last phase employs predetermined levels that have eachcells of the group programmed to their respective target states.
 12. Amethod as in 8, wherein each cell receives no more than twenty,programming pulses.
 13. A method as in anyone of claims 1-12, whereineach cell stores one of two memory states.
 14. A method as in anyone ofclaims 1-12, wherein each cell stores more than two memory states.
 15. Amethod as in anyone of claims 1-12, wherein each cell stores one ofsixteen memory states.
 16. A nonvolatile memory, comprising: an array ofmemory cells, each memory cell having a charge storage individuallyprogrammable to an associated target charge level corresponding to atarget memory state among a plurality of memory states thereof; a powerbus supplying a plurality of voltages in parallel for programming amemory cell to one of said plurality of memory states; and a parallelprogramming system for programming a group of memory cells in parallel,said parallel programming system having a plurality of programmingcircuits, one for each cell in the group, each programming circuitfurther comprising: a voltage selector selecting one of the plurality ofvoltages from said power bus, the selected voltage being a function ofthe target state of the associated memory cell such that the selectedvoltage is optimum for said programming circuit to produce a programmingvoltage for programming the memory state towards its target memorystate.
 17. A nonvolatile memory as in 16, wherein said programmingcircuit further comprising: a first programming voltage waveformgenerator coupled to receive said selected voltage to generate a firstprogramming voltage waveform having an initial amplitude which is afunction of the selected voltage; a sense amplifier for determining theprogrammed state of the memory cell; and a program inhibit circuitresponsive to the sense amplifier for inhibiting further programming ofthe cell whenever the programmed state of the memory cell has passed afirst predetermined level.
 18. A non-volatile memory as in 17, furthercomprising: a storage element for saving the last programming voltagethat causes the programmed state of the associated cell to pass thefirst predetermined level; a second programming voltage waveformgenerator responsive to said last programming voltage saved forgenerating a second programming voltage; and a controller for enablingsaid second programming voltage waveform generator after all memorycells in the group have passed the first predetermined level.